library ieee;

entity inc2 is
  port (  I   :   in bit_vector(1 downto 0);
          O   :   out bit_vector(1 downto 0));
end inc2;

architecture dataflow of inc2 is
begin
  O(0) <= not I(0);
  O(1) <= I(1) xor I(0);
end dataflow;

entity mux4to1_1 is
  port (  I0, I1, I2, I3  :   in bit;
          S               :   in bit_vector(1 downto 0);
          O               :   out bit);
end mux4to1_1;

architecture dataflow of mux4to1_1 is
begin
  O <= (I0 and not S(1) and not S(0)) or (I1 and not S(1) and S(0)) or (I2 and S(1) and not S(0)) or (I3 and S(1) and S(0));
end dataflow;

entity mux2to1_4 is
  port (I0, I1     :  in bit_vector(3 downto 0);
        S          :  in bit;
        O          :  out bit_vector(3 downto 0));
end mux2to1_4;

architecture dataflow of mux2to1_4 is
begin
  O(3) <= (I0(3) and not S) or (I1(3) and S);
  O(2) <= (I0(2) and not S) or (I1(2) and S);
  O(1) <= (I0(1) and not S) or (I1(1) and S);
  O(0) <= (I0(0) and not S) or (I1(0) and S);
end dataflow;

entity mux2to1_1 is
  port (I0, I1    : in bit;
        S         : in bit;
        O         : out bit);
end mux2to1_1;

architecture dataflow of mux2to1_1 is
begin
  O <= (I0 and not S) or (I1 and S);
end dataflow;

entity dlatch_r is
  port (D, R    :   in bit;
        CLK     :   in bit;
        Q       :   out bit);
end dlatch_r;

architecture dataflow of dlatch_r is
  component mux2to1_1
    port (I0, I1    : in bit;
          S         : in bit;
          O         : out bit);
  end component;
  
  signal w0, w1 : bit;
begin
  M1: mux2to1_1 port map (D, w1, clk, w0);
  
  w1 <= w0 and not R;
  Q <= w1;
end dataflow;

entity dff_r is
  port (D, R    :   in bit;
        CLK     :   in bit;
        Q       :   out bit);
end dff_r;

architecture dataflow of dff_r is
  component dlatch_r
    port (D, R    :   in bit;
          CLK     :   in bit;
          Q       :   out bit);
  end component;
  
  signal w0 : bit;
  signal nclk : bit;
begin
  nclk <= not CLK;
  
  DL1:  dlatch_r port map (D, R, clk, w0);
  DL2:  dlatch_r port map (w0, R, nCLK, Q);  
end dataflow;

entity dff_r_en is
  port (D, R, E :   in bit;
        CLK     :   in bit;
        Q       :   out bit);
end dff_r_en;

architecture dataflow of dff_r_en is
  component dff_r
    port (D, R    :   in bit;
          CLK     :   in bit;
          Q       :   out bit);
  end component;
  component mux2to1_1
    port (I0, I1    : in bit;
          S         : in bit;
          O         : out bit);
  end component;
  
  signal w0, w1 : bit;
begin
  M1: mux2to1_1 port map(w1, D, E, w0);
  DF: dff_r port map(w0, R, CLK, w1);
  
  Q <= w1;
end dataflow;

entity incdec4 is
  port (  A   : in  bit_vector(3 downto 0);
          D   : in  bit;
          O   : out bit_vector(3 downto 0));
end incdec4;

architecture dataflow of incdec4 is
begin
  O(0) <= not A(0);
  O(1) <= D xor A(1) xor A(0);
  O(2) <= ((A(2) xor (A(1) and A(0))) and not D) or ((A(2) xnor (A(1) or A(0))) and D);
  O(3) <= ((A(3) xor (A(2) and A(1) and A(0))) and not D) or ((A(3) xnor (A(2) or A(1) or A(0))) and D);
end dataflow;

entity dff_r_en2 is
  port  (  D    : in bit_vector(1 downto 0);
           R, E : in bit;
           CLK  : in bit;
           Q    : out bit_vector(1 downto 0));
end dff_r_en2;

architecture dataflow of dff_r_en2 is
  component dff_r_en
    port (D, R, E :   in bit;
          CLK     :   in bit;
          Q       :   out bit);
  end component;
begin
  DFF0: dff_r_en port map (D(0), R, E, CLK, Q(0));
  DFF1: dff_r_en port map (D(1), R, E, CLK, Q(1));
end dataflow;

entity dff_r_en4 is
  port (   D    : in bit_vector(3 downto 0);
           R, E : in bit;
           CLK  : in bit;
           Q    : out bit_vector(3 downto 0));
end dff_r_en4;

architecture dataflow of dff_r_en4 is
  component dff_r_en
    port (D, R, E :   in bit;
          CLK     :   in bit;
          Q       :   out bit);
  end component;
begin
  DFF0: dff_r_en port map (D(0), R, E, CLK, Q(0));
  DFF1: dff_r_en port map (D(1), R, E, CLK, Q(1));
  DFF2: dff_r_en port map (D(2), R, E, CLK, Q(2));
  DFF3: dff_r_en port map (D(3), R, E, CLK, Q(3));
end dataflow;

entity dff_r4 is
  port (   D    : in bit_vector(3 downto 0);
           R    : in bit;
           CLK  : in bit;
           Q    : out bit_vector(3 downto 0));
end dff_r4;

architecture dataflow of dff_r4 is
  component dff_r
    port (D, R    :   in bit;
          CLK     :   in bit;
          Q       :   out bit);
  end component;
begin
  DFF0: dff_r port map (D(0), R, CLK, Q(0));
  DFF1: dff_r port map (D(1), R, CLK, Q(1));
  DFF2: dff_r port map (D(2), R, CLK, Q(2));
  DFF3: dff_r port map (D(3), R, CLK, Q(3));
end dataflow;